Informatics Publishing Limited

K. V. S. H. Gayatri Sarman ¹, K. N. H. Srinivas ¹, T. Madhu ²

Affiliations
1 Sri Vasavi Engineering College, Tadepalligudem, IN
2 Swarnandhra Institute of Engineering and Technology, Seetharampuram, IN

Abstract

Automobile black box stores vital information about the date, time, speed of the vehicle, distance between the vehicles and engine temperature for every 0.5 sec. This information in the black box is useful to analyze the cause of an accident. This project was developed with two PIC microcontrollers. One microcontroller is used for capturing of the data from different sensors placed at different locations in the vehicle and second microcontroller is used for controlling of the motors. It compares the captured data with the standard data and it alerts the driver by giving the warnings whenever it finds dangerous driving levels and also if the temperature conditions of the engine exceeds the safe value. It stops the vehicle safely whenever the distance between the vehicle below the minimum range or it detects the alcohol consumed by the driver. It prevents the traffic accidents. Thus the project work ensures safety of the vehicle and the occupants.

Keywords

Automobile Black Box, Traffic, Driving Level, Vehicle Safety.

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S. Koteswara Rao ¹, M. Sailaja ², T. Madhu ³, P. Ramesh ¹

Affiliations
1 ECE Department in Regency Institute of Technology, Yanam, IN
2 ECE Department in JNTUK, Kakinada, IN
3 SIET, Narsapur, IN

Abstract

A new approach for energy efficient sensor networks that maximizes the life of the sensor networks which maintaining desired quality of service attributes related to sensed data delivery is presented. The IEEE802.15.4 as a standard for low rate wireless personal area network (LR-WPAN) is an applicative choice for wireless sensor networks. Due to the advantages of this standard and its capabilities for more specification to wireless sensor networks, we were persuaded to resolve some of its proven weaknesses in such environments. The slotted CSMA/CA method utilized in beaconsenabled mode of 802.15.4 causes an unacceptable level of energy consumption in conditions like high loads. To overcome these issues, we adopted method the capability and flexibility provided by CSMA/CA makes it work at low contention and TDMA makes it work at high loads by taking advantage of a greedy algorithm for TDMA slot allocation. Using these techniques we obtained improved results such as reduced energy consumption, improved throughput and decreased end to end delay. The new ATDMA and routing algorithm's scale well and converge fast for large scale dynamic sensors as shown by our extensive results using the Network Simulator (NS2).

Keywords

CSMA/CA, IEEE802.15.4, Energy, LR-WPAN, TDMA, Wireless Sensor Networks.

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B. KaliVara Prasad ¹, P. Satish Kumar ², B. Stephen Charles ³, T. Madhu ⁴

Affiliations
1 Department of ECE, KL University, Guntur, Andhra Pradesh, IN
2 Department of ECE, MLR Institute of Technology, Hyderabad, Andhra Pradesh, IN
3 Department of ECE, SSCET, Kurnool, Andhra Pradesh, IN
4 Department of ECE, SIET, Narsapur, Andhra Pradesh, IN

Abstract

The re-configurability of Field Programmable Gate Arrays (FPGA) plays an important role in reducing on-chip testing hardware relative to Application Specific Integrated-Circuits (ASICs). In general, fault coverage is directly related to the number and scope of test configurations that are created. To operate effectively, the specific location of the fault should be clearly identified. The fault coverage issue has been further complicated in recent years by the introduction of FPGA devices with millions of programmable switch points. This paper aims at the fault detection and location of interconnects in an FPGA. The proposed testing scheme uses a test manager, which defines a part of the chip as pattern generator and the other half as response analyzer. The chip is reconfigured several times to cover all portions of interconnect. Testing is done in two phases, phase one involves several reconfigurations intended to detect various faults in the interconnect structure. Another phase involves extensively testing the complete interconnect structure for all possible faults namely configurable interconnection points stuck on and (or) stuck off, wire stuck-at-1, wire stuck-at-0, two adjacent wires short, and wires open etc.

Keywords

FPGA, Interconnects, CLBs, Fault Diagnosis, Failure.

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N. Rajeswaran ¹, T. Madhu ², M. Suryakalavathi ³, M. Asharani ⁴

Affiliations
1 SNS College of Technology, Coimbatore, Tamilnadu, IN
2 Swarnandhra Institute of Engineering, and Technology, Narasapur, Andhra Pradesh, IN
3 Electrical and Electronics Engineering Department, JNTU University, Hyderabad, Andhrapradesh, IN
4 Electronics and Communication Engineering Department, JNTU University, Hyderabad, Andhrapradesh, IN

Abstract

Now days Hybrid Artificial Intelligence (AI) techniques such as the Genetic Algorithms (GA) and Artificial Neural Networks (ANN) are being widely used to find an optimal solution for a wide variety of complex problems including fault diagnosis and control and classification of the electrical machines. As the overall performance of the system and hence its reliability gets reduced due to imperfect and uncertain information processing, optimization techniques are to be employed to obtain the required efficiency and reliability. Hence, the hybrid AI system is tested on an Induction motor for fault diagnosis, to reduce the learning time and to obtain an efficient solution for the machine design. GA is used to select the characteristic parameters of the classifiers and the input features. For each trial, the ANNs are trained with a subset of the experimental data for known machine condition. The procedure is able to rectify all the faults especially stator fault and bearing faults of induction machine with minimum delay and maximum efficiency.

Keywords

ANN, Fault Diagnosis, Genetic Algorithm and Induction Machine.

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